Resonant circuit using variable capacitance diode

ABSTRACT

A resonance circuit having an inductor, a capacitor and a semiconductor with a junction, and means for applying a signal to the semiconductor junction. The semiconductor junction satisfies the equation: ##EQU1## where C represents the capacitance of the semiconductor junction when a voltage V is applied thereto and the junction of the semiconductor is reverse biased, C&#39; is a constant, and the inductor and capacitor are connected in series.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a resonance circuit using avariable capacitance semiconductor element, and is directed moreparticularly to a resonant circuit using a variable capacitance diode.

2. Description of the Prior Art

Recently, a so-called electronic tuner (which will be hereinafterreferred to as an ET tuner) using a variable capacitance semiconductorelement (which will be hereinafter referred to as a varicap) has beenproposed. However, the non-linearity of the varicap may cause a tuningfrequency deviation (which may be a cause of tracking error) due to thelarge amplitude operation of the local oscillator in a television tuner.Also, mutual modulcation, cross modulation and so on in an FM tuner mayresult, and for these reasons ET tuners are not used widely at present.

SUMMARY OF THE INVENTION

According to the present invention, there is proposed a resonant circuitwhich comprises an inductive means, and a capacitive means having asemiconductor junction element which satisfies the equation: ##EQU2##where C is the capacitance of the element when a voltage V is appliedand the junction of the element is reverse biased. C' is a constant andthe inductive and capacitive means are connected in series, and meansare provided for applying a signal to the element.

Accordingly, it is an object of the invention to provide a resonantcircuit free from the defects encountered in the prior art.

It is another object of the invention to provide a resonant circuitusing a capacitive element such as a varicap.

It is a further object of the invention to provide a resonant circuitusing a novel capacitive element such as a varicap which solves thenon-linearity problem of prior art varicaps.

Other objects, features and advantages of the invention will be wellunderstood by the following description taken on conjunction with theaccompanying drawings in which like reference numerals and symbols usedthrough the description indicate like elements.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram for explaining the theory of the invention;

FIG. 2 is a circuit diagram for explaining cross modulation;

FIG. 3 is a graph showing the C-V characteristics;

FIG. 4 is an enlarged cross-sectional diagram showing an example of avaricap;

FIG. 5 is a graph showing impurity profiles;

FIGS. 6A to 6E, inclusive, are diagrams showing the steps for makingvaricaps which could be used in the invention;

FIG. 7 is a graph showing the distortion ratio of varicaps;

FIGS. 8A to 8E and FIGS. 9A to 9B, inclusive, are diagrams showing thesteps for making other types of varicaps which could be used in theinvention;

FIGS. 10 to 13, inclusive, are circuit diagrams showing capacitancearrangements, which are used in the resonant circuit of the invention;

FIG. 14 is a circuit diagram showing an example of a series resonantcircuit of the invention; and

FIG. 15 is a circuit diagram illustrating an arrangement for theinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will be described with reference to the drawings.

FIG. 1 illustrates a fundamental circuit of the invention comprising aseries resonant circuit which includes an inductance L, a resistance Rand a capacitance C. It will be considered that the capacitance Cdepends upon the applied voltage or is a nonlinear capacitance. Thevoltage across the capacitance C is V and its changing value or signalcomponent δV is sufficiently small as compared with a DC bias V_(o)applied to the capacitance C, the nonlinear capacitance can be expressedin the form of a Taylor's series as follows: ##EQU3##

If the first and second terms of the above Taylor's series (1) are takenas an approximation, the following expression (2) is obtained: ##EQU4##where, ##EQU5##

In this invention, it is assumed that the influence of nonlinearity issmall and it is assumed that the following conditions exist: ##EQU6##

If the circuit shown in FIG. 1 is energized with a signal E sin (t + φ)and if the current flowing through the circuit is I, the followingdifferential equation (5) is obtained: ##EQU7##

Since the capacitance C depends upon the voltage, equation (5) is anon-linear differential equation.

In the invention, an equation (29) which gives an approximate solutionwill be described later. If equation (29) is applied to the capacitanceC in order to make equation (5) linear, and the linear equation thusobtained is compared with the linear equation which is obtained byconsidering the capacitance C in the original equation (5) constant,then a distortion component will have been considered, and thephenomenon expressed by the non-linear equation (5) is approximated aslinear. Thus, the varicap which may be the total capacitance C on whichmay form a part of the capacitance C is designed with specificparameters so as to substantially eliminate the above mentionedundesirable phenomena existing in the non-linear circuit including thecapacitance, which depends upon the voltage, in the series resonantcircuit.

First, the non-linear differential equation (5) is considered.

The current I, which flows through the circuit shown in FIG. 1 when asignal E sin (ωt + φ) is applied, is expressed as follows: ##EQU8##

The voltage V appearing across the capacitance C can be expressed asfollows: ##EQU9##

It is assumed in such oscillating condition that the voltage V isexpressed by the following equation.

    V = E.sub.1 sin ωt + V.sub.1 cos ωt + e.sub.2 sin 2ωt + v.sub.2 cos 2ωt +                                   (8)

That is, all of the combinations of the fundamental wave component arethe same as the input signal and wave components with frequencies n/mtimes ω considered. In the combinations, waves which will be effectiveoscillating ones are present and 2nd order higher harmonics areconsidered in equation (8). Further, if for the sake of brevity, sin ωt,cos ωt, sin 2ωt and cos 2ωt are expressed hereinafter as s(1), c(1),s(2) and c(2), respectively, the following equation (9) is obtained:

    V = E.sub.1 s(1) + e.sub.2 s(2) + v.sub.2 c(2)             (9)

In this case, since the exciting signal E sin (ωt + φ) has a phasefactor, in the circuit of FIG. 1, the term c(1) is unnecessary.

The equations (6) and (7) are obtained by applying a voltage V expressedby equation (12) to be described later.

First, differentiate V with respect to time t to obtain: ##EQU10##

If equation (10) is substituted into equation (2) as the factor δV, thefollowing equation (11) will be obtained: ##EQU11##

The current I can be obtained by substitution of equations (10) and (11)in equation (6). In this case, if the non-linearity is small, thefollowing conditions can be experimentally expected,

    e.sub.2 << E.sub.1, v.sub.2 << E.sub.1                     (12)

therefore, the terms following the term of 3ω become sufficiently smallthat they can be neglected. Thus, the current I becomes: ##EQU12##

Based upon equation (12), if the terms of equation (13) which includethe factors e₂ ² and v₂ ² are neglected due to the assumption that theyare small as compared with E₁ ², the following equation (14) isobtained: ##EQU13##

The first term dI/dt in the differential equation (5) will now beobtained. ##EQU14##

Next, if equation (9) is substituted into equation (7), and theresulting equation and equations (14) and (15) are substituted intoequation (5) and factors with respective to the respective frequenciesare fixed. Further, the following equation (16) is assumed. ##EQU15##Then ω, is considered to be in the vicinity of or at the resonantfrequency ω_(o).

Further, the following expressions (17) to (20) are considered:##EQU16##

From expression (18), the following expression (21) is obtained:##EQU17##

Therefore the equations (19) and (21) can be expressed as follows:##EQU18##

From the equations (22) and (23), e₂ and v₂ can be obtained as followswith the first small terms neglected. ##EQU19##

In this case, e₂ = 1/Q v₂ and hence e₂ can be neglected from a practicalmatter. Therefore, e₂ = 0.

The factors of ω will now be considered. In this case, if the valuesobtained by the expressions (24) and (25) are substituted into equation(5) and if its second terms and higher ones are neglected, the followingequation (26) is obtained: ##EQU20##

This equation (26) represents the operation of the fundamental wavecomponent.

If the differential equation (5) is similarly calculated with theassumption that the capacitance does not depend upon the amplitude, thefollowing equation (27) is obtained. ##EQU21##

As may be apparent from the insertion of ##EQU22## into equation (26)and by comparing the results with equation (27), the non-lineardifferential equation (5) can be taken as a linear equation in the casewhere a capacitance variation ΔC such as expressed as follows exists fora linear capacitance. ##EQU23##

Accordingly, if for the capacitance C the following capacitance C isused, a linear differential equation effective for the nonlineardifferential equation can be approximately obtained. ##EQU24## where##EQU25##

In other words, from equations (28) or (29) if E₁ is small,non-linearity has almost no influence. However, if the followingequation (31) or (32) is established, influence of non-linearity on theseries resonant circuit shown in FIG. 1 can be neglected. ##EQU26## or##EQU27##

The above description has given particular consideration to the trackingerror, but the problems of cross modulation will now be considered.

Cross modulation is due to non-linear capacitance in a series resonantcircuit consisting of an inductance L, a resistance R and a capacitanceC and wherein a desired signal ωd and a jamming signal ωu are appliedthereto. In this case, a consideration to that given for the trackingerror will be given. In this case, as the frequency components of thevoltage applied across the capacitance C, it is sufficient if the terms2ωd, 2ωu, ωd + ωu and ωd - ωu in addition to ωd and ωu are taken intoaccount. Further, hereinafter sin ωdt is expressed as s(1); cos ωdt asc(1); cos 2ωdt as c(2); sin ωut as s(I); cos ωut as c(I); cos 2 ω ut asc(II); cos (ωd - ωu) t as c (1-I); and cos (ωd + ω u)t as c(1+I),respectively.

Further, the applied voltage V is defined as follows:

    V = E.sub.1 sin ωdt+v.sub.2 cos 2 ωdt + W.sub.1 sin ωut + ω.sub.2 cos 2ωut + e.sub.o cos (ωd - ωu)t + e.sub.2 cos (ωd + ωu)t .tbd.  E.sub.1 s(1) + v.sub.2 c(2) + W.sub.1 s(I) = w.sub.2 c(II) + e.sub.o c(1 - I) + e.sub.2 c(1 + I) (100) ##EQU28## where factors v.sub.2.sup.2, w.sub.2.sup.2, e.sub.2.sup.2 and e.sub.o.sup.2 and their mutual products are neglected. ##EQU29##

By substituting equation (103) into equation (2) for the factor δV,equations for the respective frequency components are obtained. In thiscase, ωd and ωu are assumed to be sufficiently close to ω_(o) and Δd andΔu are assumed as follows: ##EQU30##

e₂ is obtained from the component of (ωd + ωu) where Q>> 1 is assumedand the first small term is neglected. ##EQU31##

e_(o) is obtained from the component (ωd - ωu). ##EQU32##

From the component 2ωd, v₂ is obtained as follows: ##EQU33##

From the component 2 u, w₂ is obtained as follows: ##EQU34##

It will be apparent that equations (109) and (110) are substantially thesame in form as equation (25).

From the components ωd and ωu, the following equations are derived.##EQU35##

From equations (111) and (112) and equation (29), the followingequations (113) and (114) are obtained. ##EQU36##

The component I_(d) with ωd in the current I is expressed as follows:##EQU37##

From equation (114), a minute variation (factor) εu exists in Eu, avariation factor ε_(W) of W₁ when Eu (1 + εu) is obtained, a variationfactor ε_(V) of E₁ is obtained from the equation (113), and a variationfactor ε_(d) of I_(d) is obtained from the equation (115). The crossmodulation K is given by the ratio of ε_(d) and ε_(u). In this case,ε_(w), ε_(u) << 1 and ε_(d), ε_(v) << ε_(w), ε_(u) can be assumed.

From the equation (114), the following equation (116) is derived:##EQU38##

From the equation (116), ε_(w) is expressed as follows: ##EQU39##

From the equation (113), the following equation (118) is derived.##EQU40##

Accordingly, ε_(v) is obtained as follows: ##EQU41##

From the equation (115), ε_(d) is expressed as follows:

    ε.sub.d = ε.sub.v + P*W.sub.1.sup.2 ε.sub.w (120)

From the equations (117, (119) and (120), K is expressed as follows:##EQU42##

Further, if consideration is given to the ratio K in the case where##EQU43## the following equations (122) and (123) are obtainedapproximately: ##EQU44##

Further, it is assumed that ##EQU45## which means that the amplitude ofthe jamming wave is relatively small. In general, if the crossmodulation is taken into account, the amplitude is small as compared tothe case where the tracking error is taken into account. Therefore, theabove assumption if valid.

Accordingly, the following equation (124) is obtained: ##EQU46##

If N_(u) = (QE_(u))² P*, K is expressed as follows: ##EQU47##

In order to reduce the cross modulation ratio K, P* is reduced until itapproaches zero.

According to the present invention, based upon the above considerations,P* = O is obtained or the relationship between C and V which aresolutions of the differential equation (32) namely ##EQU48## isobtained, and then a semiconductor varicap, which has the C - Vcharacteristics which satisfies the above relationship is formed.

In other words, a semiconductor varicap is constructed having theimpurity concentration showing the above C - V characteristics.

First, C is assumed as follows:

    C = C.sub.D (V.sub.o + V.sub.D).sup.n                      (200)

where C_(D) and V_(D) represent integral constants.

If the equation (200) is substituted into the equation (32), thefollowing equation (201) is derived. ##EQU49##

Therefore, the equation (200) can be rewritten as follows:

    C = C.sub.D (V.sub.o + V.sub.D).sup.-.sup.3                (202)

If desired voltage range and capacitance variation are given in theequation (202), the constants C_(D) and V_(D) are obtained,respectively, and a semiconductor varicap of P* = 0 is formed. Forexample, if it is assumed that when V_(o) = 2 volts, C = 15_(p) F andthat when V_(o) = 25 volts, C = 2.25_(p) F, C_(D) and V_(D) become asfollows:

    C.sub.D = 2.66 × 10.sup.15 (.sub.p F.sup.V.spsp.3)

    V.sub.D = 24.1 (volts)

The C - V characteristic of the varicap in this case is shown by curve300 in the graph of FIG. 3.

Consideration will now be given as to how to obtain an impurityconcentration to produce a varicap with the above C - V characteristic.Now, it is assumed that, in a semiconductor varicap having a PN junctionJ, the position of the PN junction J is taken as O and the expansion ofits depletion layer from the position O is taken as x_(m), as shown inFIG. 4. It is also assumed that the impurity concentration distributionin the expansion direction of the depletion layer is N(x). An appliedvoltage V_(o) to the varicap is expressed as follows: ##EQU50## whereφ_(D) represents an expansion potential difference, ε the dielectricconstant of the semiconductor and q an electrical charge.

V_(o) will be obtained from the equation (202).

If the area of the junction J is taken as S, C is expressed as follows:##EQU51##

Therefore, the following equation (205) is obtained. ##EQU52##

A sufficient solution will exist if the equations (203) and (205) havethe same form.

The following equation (206) is assumed and substituted into equation(203).

    N(x) = Ax.sup.-.sup.n                                      (206) ##EQU53##

From the equations (205) and (207), A is expressed as follows: ##EQU54##

Therefore, N(x) is expressed as follows: ##EQU55##

If, in the above example, the area S is taken as 3.9 × 10⁻ ⁴ cm² (S =3.9 × 10⁻ ⁴ cm²), the impurity concentration distribution N(x) isexpressed as follows:

    N(x) = 4.16 × 10.sup.9 x.sub.m .sup.-5/3

This impurity concentration distribution is shown by a curve 301 in thegraph of FIG. 5.

The ideal impurity concentration distribution curve 301 has its peakvalue at a depth of about 0.2 μ(microns) from the position of thejunction (x = 0) and the expansion width of the depletion x_(mo)corresponding to V = 0 exists at about 0.2μ, the same as the peak value.This means that when the external voltage is zero, the depletion layermust be expanded to that position due to the diffusion potentialdifference. The C - V characteristic and impurity concentrationdistribution of an example of varicaps now on market are shown by curve302 in FIG. 3 and by curve 303 in FIG. 5.

As is apparent from a comparison of the curves 301 and 303, the idealcurve 301 has the peak at the depth of 0.2μ and the peak value of itsimpurity concentration is about 1.2 × 10¹⁷ atom/cm³, while that of theprior art is about ˜ 6 × 10¹⁶ atom/cm³. If the C - V characteristiccurves 300 and 302 are compared, there is a great difference betweenthem at low voltages. This illustrates the fact that tuners which usethe prior art semiconductor varicaps have large tracking errorsparticularly at low voltages.

Therefore, a semiconductor varicap, which is used in the resonantcircuit of this invention, has a semiconductor layer with a sufficientlylow impurity concentration formed on the surface of a semiconductorsubstrate wherein a junction is formed, and the depletion layer of thejunction is expanded to a position which results in the peak value of apredetermined impurity concentration when V =O.

An example of the method for making the above varicap of the inventionwill now be described with reference to FIGS. 6A to 6E. As shown in FIG.6A, a semiconductor substrate of one conductivity type, for example, asingle crystalline silicon substrate 1 with an N-type impurityconcentration of ˜10¹⁹ atom/cm³ is prepared.

As shown in FIG. 6B, a semiconductor layer 2 of high impurityconcentration with the same conductivity type as that of the substrate1, which semiconductor layer 2 serves to support in ohmic contact anelectrode (described later), is formed on one surface 1a of thesubstrate 1, for example, by diffusion, and an impurity of the sameconductivity type as that of the substrate 1 is selectively diffusedtherein from its other surface 1b to form a diffusion region 3. In thiscase, the diffusion region 3 is so formed that its impurityconcentration distribution in the direction from the surface 1b of thesubstrate 1 to its interior is greater than x_(mo) of curve 301 in FIG.5. In FIG. 6B, reference numeral 4 indicates a diffusion mask made of,for example, SiO₂ which is used for making the diffusion region 3 andits diffusion window is formed with a similar oxidized layer when theregion 3 is formed by diffusion.

Then, as shown in FIG. 6C, the diffusion mask 4 on the surface 1b andthe oxidized layer formed thereon are removed, and thereafter on thesurface 1b there is formed, for example, by an epitaxial method, anintrinsic semiconductor layer or a semiconductor layer with the same ordifferent conductivity type as that of the substrate 1. For example, anintrinsic silicon layer 5 is formed which is a base 6.

As shown in FIG. 6D, on the surface of the base 6, there is formed by awell known technique an insulating layer 7 such as SiO₂ which may be adiffusion mask. A diffusion window is selectively formed through theinsulating layer 7 at the position opposite the region 3, and then animpurity with a different conductivity from that of the region 3 isdiffused through the window into the layer 5 at a high impurityconcentration to form therein a diffusion region 8, for example, ofP-type conductivity and hence to form a rectifying junction J. In thiscase, the junction J is formed in the intrinsic or low impurityconcentration semiconductor layer 5 and the depth of the region 8 andthe thickness of the layer 5 are so selected that a distance d betweenthe junction J and the region 3 of the predetermined impurityconcentration distribution is selected to be in the range between0.1˜0.5μ, for example 0.2μ.

As shown in FIG. 6E, electrodes 9 and 10 are formed in ohmic contactwith the regions 8 and 2, respectively. Thus, a semiconductor varicap isformed. With such a varicap, the region 3 is diffused into the substrate1 from the surface 1b and has its maximum impurity concentration at thesurface 1b, while the junction J is formed in the intrinsic orsufficiently low impurity concentration semiconductor layer 5 and thejunction J is separated from the high impurity concentration region 3 orthe surface 1b by 0.1˜0.5μ, for example, 0.2μ. Therefore, its depletionlayer goes to the surface 1b which shows a peak impurity concentrationwhen V = O. Accordingly, if a voltage is applied from the surface 1b tothe junction J to increase the reverse voltage and if the impurityconcentration distribution of the region 3 is the distribution shown bythe curve 301 in FIG. 5, the varicap has a characteristic which has themaximum concentration at x = x_(mo) to obtain the ideal profile.

FIG. 7 is a graph illustrating the measured results of voltages appliedto the varicap versus its variation of capacitive ratio Δc/C . In thegraph of FIG. 7, a line 400 represents an ideal characteristic, a curve401 the characteristic of the varicap of the invention, and a curve 402that of a prior art varicap. As is apparent from FIG. 7, the varicap ofthe invention has a characteristic close to the ideal characteristic.

In the varicap shown in FIGS. 6A to 6E, the rectifying junction J isformed by the PN junction. However, it is possible that the diffusionregion 8 can be omitted and a metal layer coated on the semiconductorlayer 5 opposite the region 3 to form a Schottky barrier to thereby forma Schottky barrier type variable capacitance diode.

Further, in the embodiment shown in FIGS. 6A to 6E, the intrinsic orsufficiently low impurity concentration semiconductor layer 5 is formedby the epitaxial growth method, but the layer 5 can be formed by an ioninjection method. An example using the ion injection method will bedescribed with reference to FIGS. 8A to 8E.

As shown in FIG. 8A, a semiconductor body, for example, a silicon body 6with one conductivity type, for example, an N-type with an impurityconcentration of about ˜10¹⁹ atoms/cm³ is prepared.

As shown in FIG. 8B, an impurity with the same conductivity type as thatof the body 6 is diffused, for example, into the body 6 from its onesurface 6a at a high impurity concentration to form a high impurityconcentration semiconductor layer 2. An impurity of the conductivitytype as the body 6 is selectively, for example, diffused into the body 6from its other surface 6b to form a diffusion region 3 and hence to forma substrate region 1 between the region 3 and the semiconductor layer 2.In FIG. 8B, reference numeral 4 indicates a diffusion mask whosediffusion window is covered with an oxide layer which is formed duringthe diffusion of the region 3.

Then, as shown in FIG. 8C, a window is bored through the diffusion mask4 opposite the region 3, and impurity ions with a different conductivitytype from that of region 3 or P-type conductivity is injected into theregion 3 by the injection method to cancel the N-type impurity at thesurface of the region 3 and hence to form a semiconductor layer 5 ofsubstantially intrinsic or low impurity concentration.

As shown in FIGS. 8D and 8E, the PN junction J is formed in a mannersimilar to that described with respect to FIGS. 6D and 6E or theSchottky barrier is formed to form the semiconductor varicap. In FIGS.8D and 8E, the reference numerals the same as those used in FIGS. 6D and6E represent similar elements, and their description will be omitted.Further, in the embodiment shown in FIGS. 8A to 8E, the distance dbetween the junction J and the region 3 is selected between 0.1μ and0.5μ and desirably 0.2μ.

In the semiconductor varicap of the invention made as mentioned above,the junction J is also formed in the intrinsic or low impurityconcentration semiconductor layer 5, the distance d between the junctionJ and the region 3 is, for example, 2μ, and the depletion layer isexpanded to the position where the region 3 contacts the semiconductorlayer 5, so that the position x_(mo) of the expanded depletion layer atV = O exists at the highest impurity concentration.

In the embodiment shown in FIGS. 6A to 6E, the epitaxial or intrinsic orsufficiently low impurity concentration semiconductor layer 5 is formedon the surface of the substrate, but it is possible that apolycrystalline semiconductor, for example, polycrystalline siliconlayer can be formed on the surface of the substrate as the semiconductorlayer 5. An example of such construction will be described withreference to FIGS. 9A to 9E.

As shown in FIGS. 9A and 9B, processes which are the same as thosedescribed with reference to FIGs. 6A and 6B are carried out. Thereafter,as shown in FIG. 9C, a semiconductor layer 5 made of a polycrystallinesilicon without being doped and with almost no impurity and having ahigh resistance is grown on the substrate 1 by a well known technique.Then, as shown in FIGS. 9D and 9E, the same processes as those describedwith reference to FIGS. 6D and 6E are carried out. In FIGS. 9A to 9E,reference numerals the same as those used in FIGS. 6A to 6D designatethe same elements.

In the embodiment of FIGS. 9A through 9D, since the state of theelectric field in the polycrystalline silicon is substantially the sameas that in the single crystalline silicon, this semiconductor varicaphas the same characteristics as those of the semiconductor varicapdescribed with reference to FIGS. 6A to 6E.

The varicaps described above are used as the capacitance in the seriesresonant circuit shown in FIG. 1. However, in a practical circuit, thevaricap is connected in various manners. In this case, the capacitancesystem is a non-linear capacitance and β/α, γ/α or P are obtained fromthe factors of the Taylor's series for the capacitance.

A typical example of the capacitance system will now be considered. Thecapacitance system, in which a varicap C is connected in series to acapacitance C_(S) as shown in FIG. 10, will be first considered. If itis assumed that an AC voltage V₁ is applied across the combinedcapacitance system, an AC voltage v will be applied across the varicap Cwhich can be expressed as follows: ##EQU56##

The characteristic of the varicap can be expressed as follows if thevoltage across the varicap is v. ##EQU57##

Accordingly, the capacitance C_(t) of the capacitance system shown inFIG. 10 is expressed as follows: ##EQU58##

Now, the expansion factors β'/α' and γ'/α' will be obtained. ##EQU59##

The differential equation which will make P*' zero is as follows:##EQU60##

The functional relationship between C and V which are solutions of theabove differential equation are obtained, and then it is sufficient toconstruct a varicap which as the C - V characteristic which solves thisrelationship.

Next, a capacitance system, in which the varicap C is connected inparallel with a capacitance C_(p) as shown in FIG. 11, will beconsidered. In this case, the capacitance C_(t) of the whole capacitancesystem is expressed as follows:

    C.sub.t = C.sub.p + C                                      (410) ##EQU61##

Then, in a manner as described above, the following equations can bederived. ##EQU62##

The differential equation which will make P* zero is as follows:##EQU63## where C' = C_(o) + C_(p).

Then, the functional relationship between C and V which are solutions ofthe differential equation are obtained and then a varicap is constructedwhich has the desired C - V characteristic.

A capacitance system, in which the capacitance C_(s) is connected inseries to the varicap C and the capacitance C_(p) is connected inparallel to the series connection of C_(s) and C as shown in FIG. 12,will now be considered. In this case, the capacitance C_(t) of the wholecapacitance system is expressed as follows: ##EQU64##

The capacitance system of FIG. 12 can be considered as a combination ofthe ones shown in FIGS. 10 and 11, and the following expressions areobtained: ##EQU65##

The differential equation which will make P* zero is as follows:##EQU66##

Then, the functional relationship between C and V which are solutions ofthe above differential equation are obtained, and a varicap isconstructed which has the desired C - V characteristic.

A circuit including the varicap C, capacitances C_(s) and C_(p)connected as shown in FIG. 13 will now be considered.

If the characteristics of the varicap C is expressed as follows:##EQU67## The capacitance C_(t) of the whole circuit shown in FIG. 13 isexpressed as follows: ##EQU68##

The differential circuit which will make P* zero is expressed asfollows: ##EQU69##

Then, the functional relationship between C and V which are solutions ofthe above differential equation are obtained, and a varicap isconstructed which has the desired C - V characteristic.

As may be apparent from the foregoing, with the resonance circuit of thepresent invention, a varicap is used which has the C-V characteristicwhich satisfies the differential equation ##EQU70## where C' is aconstant determined by the manner of connection of the capacitancesystem and C. C' = C when the capacitance system consists of onevaricap. The solution of the differential equation makes the fundamentaldistortion P* or ##EQU71## zero.

The resonant circuit of the invention can avoid defects such as trackingerror, cross demodulation and so on which may be caused bynon-linearity, so that the resonant circuit of the invention contributesmuch to the practical use of electronic tuning circuits and makes thempractical.

The above examples use one varicap in their capacitance systems of theseries resonance circuits. However, a series resonance circuit of acapacitance system, in which two varicaps C₁ and C₂ are connected backto back and useable in an FM tuner is shown in FIG. 14. In this example,a bias voltage of V_(o) - v/2 is applied across the first varicap C₁ anda bias voltage of V_(o) + v/2 is applied across the second varicap C₂.Accordingly, the total capacitance C_(t) of the capacitance system canbe calculated as follows: ##EQU72##

If it is assumed that 2C_(o) = α₁ = α₂ =α, β₁ = β₂ = β, and γ₁ = γ₂ = γwhich means the same value varicaps are connected in series, thecapacitance C_(t) is expressed as follows: ##EQU73##

If in the above expression the capacitance shift is small, thecapacitance C_(t) is expressed as follows. ##EQU74##

Accordingly, the distortion P_(d) is expressed as follows: ##EQU75##

The differential equation which will make P*_(d) zero can be obtainedand is: ##EQU76##

Accordingly, if the varicap is made to have a C - V characteristic whichsatisfies the differential equation (431), the distortion of the varicapwill be reduced to a minimum.

The above equation (43) can be changed as follows: ##EQU77##

Therefore, by reducing ##EQU78## to zero, the distortion P_(d) can besubstantially reduced. In other words, if the varicap is made to have aC - V characteristic approximately satisfying ##EQU79## it reduces thedistortion.

When two varicaps are connected in a forward manner in the capacitancesystem, the distortion P_(d) * ' can be expressed as follows: ##EQU80##

A parallel resonance circuit is shown in FIG. 15. In FIG. 15, referencenumerals 500 indicate by-pass capacitors. In this example, since an ACbias v is applied to the varicaps C₁ and C₂ in reverse phase, thefollowing expressions can be derived.

    C.sub.1 = C βv + γv.sup.2

    C.sub.2 = C-βv + γv.sup.2

    C.sub.t = 2C + 2γv.sup.2

    = 2C (1 + γv.sup.2)

Accordingly, in order to cancel the non-linear distortion, the followingequation must be satisfied.

    γ = 0

    d.sup.2 C /dv.sup.2 = 0 C = aV + b

It may be apparent that many modifications and variations could beeffected by one skilled in the art without departing from the spirits orscope of the novel concepts of the present invention.

I claim as my invention:
 1. A resonance circuit comprising:a. aninductive means; b. a capacitive means having a semiconductor junctionelement which includes a layer of intrinsic semiconductor materialadjacent the junction and which satisfies the equation ##EQU81## where Cis the capacitance of said element when a voltage V is applied theretoand a junction of said junction element is reverse biased and C' is aconstant, c. means for applying a signal to said element, said C' isequal to said C, and C = C_(D) (V + V_(D))⁻ ³ is satisfied where C_(D)and V_(D) are constants, and said element has an impurity concentrationproportional to 5/x 3, where x is the distance from said junction, and alow doping profile exists in the neighborhood of said junction.
 2. Aresonance circuit according to claim 1, in which said capacitive meanshas at least one capacitor connected in series and/or parallel to saidelement, and C' comprises the effective capacitance of said element andsaid capacitor.
 3. A resonant circuit according to claim 1 wherein saidcapacitive means has at least one additional capacitor connected inseries to said semiconductor junction element and C' comprises theeffective capacitance of said semiconductor junction element and saidadditional capacitor.
 4. A resonant circuit according to claim 1 whereinsaid capacitive means has at least one additional capacitor connected inparallel to said semiconductor junction element and C' comprises theeffective capacitance of said semiconductor junction element and saidadditional capacitor.
 5. A resonance circuit comprising:a. an inductivemeans; b. a capacitive means having two semiconduction junction elementsand includes layers of intrinsic semiconduction material adjacent thejunctions and connected in series and in opposite directions, c. Avoltage source connected to said capacitive means, said elementsatisfying the equation ##EQU82## where C is the capacitance of saidelement when a voltage V is applied from said voltage source and ajunction of said element is reversely biased and C' is a constant; andmeans for applying a signal to said elements.
 6. A resonant circuitcomprising,a. an inductor, b. a capacitive means connected to saidinductor, c. a voltage source connectable to said capacitive means, d.said capacitive means comprising a semiconductor junction element andincludes a layer of intrinsic semiconductor material adjacent thejunction and which satisfies the equation ##EQU83## where C is thecapacitance of said element when a voltage V is applied thereto fromsaid voltage source and a junction of said semiconductor element isreverse biased and C' is a constant.
 7. A resonant circuit according toclaim 6 in which C' is equal to C and C = C_(D) (V + V_(D))⁻ ³ issatisfied where C_(D) and V_(D) are constants.
 8. A resonant circuitaccording to claim 7 in which said semiconductor junction element has animpurity concentration proportional to X⁻ ^(5/3) where X is the distancefrom said junction and a low doping profile exists near said junction.